1. Field of the Invention
The present invention relates to planarization for semiconductor structures or device fabrication.
2. Description of the Related Art
This section provides background information and introduces information related to various aspects of the disclosure that are described and/or claimed below. These background statements are not admissions of prior art.
Integration of lattice-mismatched semiconductor materials is one path to high performance devices such as complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FET) due to their high carrier mobility. For example, the heterointegration of lattice-mismatched semiconductor materials with silicon will be useful for a wide variety of device applications. One heterointegration method involves creation of confined regions of lattice-mismatched semiconductor materials on a silicon substrate. However, planarization is typically required for device fabrication. Chemical mechanical polishing (CMP) of the selected lattice-mismatched semiconductor materials is an option to smooth the surface of the material. Low material removal rates are needed, and creation of dishing or surface impurities must be avoided. Thus, there exists a need to planarize a surface of lattice-mismatched materials in a confined or selectively grown area (e.g., an active region of crystalline materials).